This invention relates to the distribution of large numbers of clocks or other signals on a programmable logic device. In particular, this invention relates to the distribution of clocks or other signals with acceptable skew without unduly increasing the number of low-skew clock trees.
In the early days of programmable logic devices, global clock signals or other global signals could be distributed using the general global routing resources of the device. Device sizes were small enough that skew was not a particular concern. However, as programmable logic devices became larger, skew became a concern. One solution to the problem of global clock skew or other global signal skew was the development of a clock tree network commonly referred to as an “H-tree,” which allowed a clock signal or other global signal to be introduced at a single point on a device and be delivered to all points on the device with minimal skew.
However, as programmable logic device sizes have continued to increase, the amount of metallization resources required to provide H-tree clock networks has increased dramatically. At the same time, the number of clocks and other signals to be distributed widely across a device also has increased dramatically. For example, PLDs frequently incorporate high-speed serial interfaces to accommodate high-speed signalling standards. Clocks derived from such interfaces using clock-data recovery (CDR) or dynamic phase alignment (DPA) techniques may have to be distributed throughout a PLD to wherever the associated data is being used or processed.
It would be desirable to be able to efficiently distribute clocks and other signals in a programmable logic device.